 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| d a t a sh eet product speci?cation supersedes data of 1997 mar 28 file under integrated circuits, ic12 1997 jul 15 integrated circuits pcf8583 clock/calendar with 240 8-bit ram
1997 jul 15 2 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 contents 1 features 2 general description 3 quick reference data 4 ordering information 5 block diagram 6 pinning 7 functional description 7.1 counter function modes 7.2 alarm function modes 7.3 control/status register 7.4 counter registers 7.5 alarm control register 7.6 alarm registers 7.7 timer 7.8 event counter mode 7.9 interrupt output 7.10 oscillator and divider 7.11 initialization 8 characteristics of the i 2 c-bus 8.1 bit transfer 8.2 start and stop conditions 8.3 system configuration 8.4 acknowledge 9i 2 c-bus protocol 9.1 addressing 9.2 clock/calendar read/write cycles 10 limiting values 11 handling 12 dc characteristics 13 ac characteristics 14 application information 14.1 quartz frequency adjustment 14.1.1 method 1: fixed osci capacitor 14.1.2 method 2: osci trimmer 14.1.3 method 3: 15 package outlines 16 soldering 16.1 introduction 16.2 dip 16.2.1 soldering by dipping or by wave 16.2.2 repairing soldered joints 16.3 so 16.3.1 reflow soldering 16.3.2 wave soldering 16.3.3 repairing soldered joints 17 definitions 18 life support applications 19 purchase of philips i 2 c components 1997 jul 15 3 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 1 features i 2 c-bus interface operating supply voltage: 2.5 v to 6 v clock operating supply voltage (0 to +70 c): 1.0 v to 6.0 v 240 8-bit low-voltage ram data retention voltage: 1.0 v to 6 v operating current (at f scl = 0 hz): max. 50 m a clock function with four year calendar universal timer with alarm and overflow indication 24 or 12 hour format 32.768 khz or 50 hz time base serial input/output bus (i 2 c) automatic word address incrementing programmable alarm, timer and interrupt function slave address: C read: a1 or a3 C write: a0 or a2. 2 general description the pcf8583 is a clock/calendar circuit based on a 2048-bit static cmos ram organized as 256 words by 8 bits. addresses and data are transferred serially via the two-line bidirectional i 2 c-bus. the built-in word address register is incremented automatically after each written or read data byte. address pin a0 is used for programming the hardware address, allowing the connection of two devices to the bus without additional hardware. the built-in 32.768 khz oscillator circuit and the first 8 bytes of the ram are used for the clock/calendar and counter functions. the next 8 bytes may be programmed as alarm registers or used as free ram space. the remaining 240 bytes are free ram locations. 3 quick reference data 4 ordering information symbol parameter condition min. typ. max. unit v dd supply voltage operating mode i 2 c-bus active 2.5 - 6.0 v i 2 c-bus inactive 1.0 - 6.0 v i dd supply current operating mode f scl = 100 khz -- 200 m a i ddo supply current clock mode f scl = 0 hz; v dd =5v - 10 50 m a f scl = 0 hz; v dd =1v - 210 m a t amb operating ambient temperature range - 40 - +85 c t stg storage temperature range - 65 - +150 c type number package name description version pcf8583p dip8 plastic dual in-line package; 8 leads (300 mil) sot97-1 PCF8583T so8 plastic small outline package; 8 leads; body width 7.5 mm sot176-1 1997 jul 15 4 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 5 block diagram fig.1 block diagram. handbook, full pagewidth mrb001 control/status hundredth of a second seconds minutes hours year/date weekdays/months timer alarm control alarm registers or ram ram (240 8) divider 1 : 256 or 100 : 128 100 hz pcf8583 oscillator 32.768 khz control logic power-on reset address register osci osco int a0 sda ff 0f 08 07 01 00 i 2 c-bus interface v dd 1 2 7 8 3 scl 6 5 v ss 4 6 pinning symbol pin description osci 1 oscillator input, 50 hz or event-pulse input osco 2 oscillator output a0 3 address input v ss 4 negative supply sda 5 serial data line scl 6 serial clock line int 7 open drain interrupt output (active low) v dd 8 positive supply handbook, halfpage 1 2 3 4 8 7 6 5 pcf8583p PCF8583T v ss osci osco scl sda v dd mrb014 int a0 fig.2 pinning diagram. 1997 jul 15 5 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 7 functional description the pcf8583 contains a 256 by 8-bit ram with an 8-bit auto-increment address register, an on-chip 32.768 khz oscillator circuit, a frequency divider, a serial two-line bidirectional i 2 c-bus interface and a power-on reset circuit. the first 16 bytes of the ram (memory addresses 00 to 0f) are designed as addressable 8-bit parallel special function registers. the first register (memory address 00) is used as a control/status register. the memory addresses 01 to 07 are used as counters for the clock function. the memory addresses 08 to 0f may be programmed as alarm registers or used as free ram locations, when the alarm is disabled. 7.1 counter function modes when the control/status register is programmed, a 32.768 khz clock mode, a 50 hz clock mode or an event-counter mode can be selected. in the clock modes the hundredths of a second, seconds, minutes, hours, date, month (four year calendar) and weekday are stored in a bcd format. the timer register stores up to 99 days. the event counter mode is used to count pulses applied to the oscillator input (osco left open-circuit). the event counter stores up to 6 digits of data. when one of the counters is read (memory locations 01 to 07), the contents of all counters are strobed into capture latches at the beginning of a read cycle. therefore, faulty reading of the count during a carry condition is prevented. when a counter is written, other counters are not affected. 7.2 alarm function modes by setting the alarm enable bit of the control/status register the alarm control register (address 08) is activated. by setting the alarm control register a dated alarm, a daily alarm, a weekday alarm or a timer alarm may be programmed. in the clock modes, the timer register (address 07) may be programmed to count hundredths of a second, seconds, minutes, hours or days. days are counted when an alarm is not programmed. whenever an alarm event occurs the alarm flag of the control/status register is set. a timer alarm event will set the alarm flag and an overflow condition of the timer will set the timer flag. the open drain interrupt output is switched on (active low) when the alarm or timer flag is set (enabled). the flags remain set until directly reset by a write operation. when the alarm is disabled (bit 2 of control/status register = 0) the alarm registers at addresses 08 to 0f may be used as free ram. 7.3 control/status register the control/status register is defined as the memory location 00 with free access for reading and writing via the i 2 c-bus. all functions and options are controlled by the contents of the control/status register (see fig.3). 7.4 counter registers in the clock modes 24 h or 12 h format can be selected by setting the most significant bit of the hours counter register. the format of the hours counter is shown in fig.5. the year and date are packed into memory location 05 (see fig.6). the weekdays and months are packed into memory location 06 (see fig.7). when reading these memory locations the year and weekdays are masked out when the mask flag of the control/status register is set. this allows the user to read the date and month count directly. in the event-counter mode events are stored in bcd format. d5 is the most significant and d0 the least significant digit. the divider is by-passed. in the different modes the counter registers are programmed and arranged as shown in fig.4. counter cycles are listed in table 1. 1997 jul 15 6 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 fig.3 control/status register. handbook, full pagewidth memory location 00 reset state: 0000 0000 timer flag (50% duty factor seconds flag if alarm enable bit is 0) alarm flag (50% duty factor minutes flag if alarm enable bit is 0) alarm enable bit: 0 alarm disabled: flags toggle alarm control register disabled (memory locations 08 to 0f are free ram space) 1 enable alarm control register (memory location 08 is the alarm control register) mask flag: 0 read locations 05 to 06 unmasked 1 read date and month count directly function mode : 00 clock mode 32.768 khz 01 clock mode 50 hz 10 event-counter mode 11 test modes hold last count flag : 0 count 1 store and hold last count in capture latches stop counting flag : 0 count pulses 1 stop counting, reset divider 76543210 msb lsb mrb017 1997 jul 15 7 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 handbook, full pagewidth control/status hundredth of a second 1/10 s seconds minutes hours year/date weekday/month timer 10 s 10 min 10 h 10 day 10 month 10 day 1/100 s 1 s 1 min 1 h 1 day 1 month 1 day alarm control hundredth of a second 1/10 s 1/100 s alarm seconds alarm minutes alarm hours alarm month alarm timer alarm date control/status d1 d3 d5 free free free timer t1 alarm control alarm alarm d1 d3 d5 d0 d2 d4 t0 d0 d2 d4 free free free alarm timer free ram free ram 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f clock modes event counter mrb015 fig.4 register arrangement. 1997 jul 15 8 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 fig.5 format of the hours counter. h andbook, full pagewidth 76543210 msb lsb mrb002 memory location 04 (hours counter) reset state: 0000 0000 unit hours bcd ten hours (0 to 2 binary) am/pm flag: 0 am 1 pm format: 0 24 h format, am/pm flag remains unchanged 1 12 h format, am/pm flag will be updated fig.6 format of the year/date counter. handbook, full pagewidth 7 65 432 10 msb lsb mrb003 memory location 05 (year/date) reset state: 0000 0001 unit days bcd ten days (0 to 3 binary) year (0 to 3 binary, read as 0 if the mask flag is set) fig.7 format of the weekdays/month counter. handbook, full pagewidth 76 543 210 msb lsb mrb004 memory location 06 (weekdays/months) reset state: 0000 0001 unit months bcd ten months weekdays (0 to 6 binary, read as 0 if the mask flag is set) 1997 jul 15 9 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 table 1 cycle length of the time counters, clock modes unit counting cycle carry to next unit contents of the month counter hundredths of a second 00 to 99 99 to 00 - seconds 00 to 59 59 to 00 - minutes 00 to 59 59 to 00 - hours (24 h) 00 to 23 23 to 00 - hours (12 h) 12 am -- 01 am to 11 am -- 12 pm -- 01 pm to 11 pm 11 pm to 12 am - date 01 to 31 31 to 01 1, 3, 5, 7, 8, 10 and 12 01 to 30 30 to 01 4, 6, 9 and 11 01 to 29 29 to 01 2, year = 0 01 to 28 28 to 01 2, year = 1, 2 and 3 months 01 to 12 12 to 01 - year 0 to 3 -- weekdays 0 to 6 6 to 0 - timer 00 to 99 no carry - 7.5 alarm control register when the alarm enable bit of the control/status register is set (address 00, bit 2) the alarm control register (address 08) is activated. all alarm, timer, and interrupt output functions are controlled by the contents of the alarm control register (see fig.8). 7.6 alarm registers all alarm registers are allocated with a constant address offset of hexadecimal 08 to the corresponding counter registers (see fig.4, register arrangement). an alarm signal is generated when the contents of the alarm registers matches bit-by-bit the contents of the involved counter registers. the year and weekday bits are ignored in a dated alarm. a daily alarm ignores the month and date bits. when a weekday alarm is selected, the contents of the alarm weekday/month register will select the weekdays on which an alarm is activated (see fig.9). remark : in the 12 h mode, bits 6 and 7 of the alarm hours register must be the same as the hours counter. 1997 jul 15 10 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 fig.8 alarm control register; clock mode. handbook, full pagewidth memory location 08 reset state: 0000 0000 timer function : 000 no timer 001 hundredths of a second 010 seconds 011 minutes 100 hours 101 days 110 not used 111 test mode, all counters in parallel (factory use only) timer interrupt enable : 0 timer flag, no interrupt 1 timer flag, interrupt clock alarm function : 00 no clock alarm 01 daily alarm 10 weekday alarm 11 dated alarm timer alarm enable : 0 no timer alarm 1 timer alarm alarm interrupt enable : (valid only when 'alarm enable' in control / status register is set 0 alarm flag, no interrupt 1 alarm flag, interrupt 7 654 321 0 msb lsb mrb005 1997 jul 15 11 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 fig.9 selection of alarm weekdays. handbook, full pagewidth 76543210 msb lsb mrb006 memory location 0e (alarm weekday / month) weekday 0 enabled when set weekday 1 enabled when set weekday 2 enabled when set weekday 3 enabled when set weekday 4 enabled when set weekday 5 enabled when set weekday 6 enabled when set not used 7.7 timer the timer (location 07) is enabled by setting the control/status register = xx0x x1xx. the timer counts up from 0 (or a programmed value) to 99. on overflow, the timer resets to 0. the timer flag (lsb of control/status register) is set on overflow of the timer. this flag must be reset by software. the inverted value of this flag can be transferred to the external interrupt by setting bit 3 of the alarm control register. additionally, a timer alarm can be programmed by setting the timer alarm enable (bit 6 of the alarm control register). when the value of the timer equals a pre-programmed value in the alarm timer register (location 0f), the alarm flag is set (bit 1 of the control/status register). the inverted value of the alarm flag can be transferred to the external interrupt by enabling the alarm interrupt (bit 6 of the alarm control register). resolution of the timer is programmed via the 3 lsbs of the alarm control register (see fig.11, alarm and timer interrupt logic diagram). 7.8 event counter mode event counter mode is selected by bits 4 and 5 which are logic 1, 0 in the control/status register. the event counter mode is used to count pulses externally applied to the oscillator input (osco left open-circuit). the event counter stores up to 6 digits of data, which are stored as 6 hexadecimal values located in locations 1, 2, and 3. thus, up to 1 million events may be recorded. an event counter alarm occurs when the event counter registers match the value programmed in locations 9, a, and b, and the event alarm is enabled (bits 4 and 5 which are logic 0, 1 in the alarm control register). in this event, the alarm flag (bit 1 of the control/status register) is set. the inverted value of this flag can be transferred to the interrupt pin (pin 7) by setting the alarm interrupt enable in the alarm control register. in this mode, the timer (location 07) increments once for every one, one-hundred, ten thousand, or 1 million events, depending on the value programmed in bits 0, 1 and 2 of the alarm control register. in all other events, the timer functions are as in the clock mode. 7.9 interrupt output the conditions for activating the open-drain n-channel interrupt output int (active low) are determined by appropriate programming of the alarm control register. these conditions are clock alarm, timer alarm, timer overflow, and event counter alarm. an interrupt occurs when the alarm flag or the timer flag is set, and the corresponding interrupt is enabled. in all events, the interrupt is cleared only by software resetting of the flag which initiated the interrupt. 1997 jul 15 12 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 fig.10 alarm control register, event-counter mode. handbook, full pagewidth memory location 08 reset state: 0000 0000 timer function : 000 no timer 001 units 010 100 011 10 000 100 1 000 000 101 not allowed 110 not allowed 111 test mode, all counters in parallel timer interrupt enable : 0 timer flag, no interrupt 1 timer flag, interrupt clock alarm function : 00 no event alarm 01 event alarm 10 not allowed 11 not allowed timer alarm enable : 0 no timer alarm 1 timer alarm alarm interrupt enable : 0 alarm flag, no interrupt 1 alarm flag, interrupt 7 654 321 0 msb lsb mrb007 in the clock mode, if the alarm enable is not activated (alarm enable bit of control/status register is logic 0), the interrupt output toggles at 1 hz with a 50% duty cycle (may be used for calibration). this is the default power-on state of the device. the off voltage of the interrupt output may exceed the supply voltage, up to a maximum of 6.0 v. a logic diagram of the interrupt output is shown in fig.11. 7.10 oscillator and divider a 32.768 khz quartz crystal has to be connected to osci (pin 1) and osco (pin 2). a trimmer capacitor between osci and v dd is used for tuning the oscillator (see quartz frequency adjustment). a 100 hz clock signal is derived from the quartz oscillator for the clock counters. in the 50 hz clock mode or event-counter mode the oscillator is disabled and the oscillator input is switched to a high impedance state. this allows the user to feed the 50 hz reference frequency or an external high speed event signal into the input osci. 7.11 initialization when power-up occurs the i 2 c-bus interface, the control/status register and all clock counters are reset. the device starts time-keeping in the 32.768 khz clock mode with the 24 h format on the first of january at 0.00.00: 00. a 1 hz square wave with 50% duty cycle appears at the interrupt output pin (starts high). it is recommended to set the stop counting flag of the control/status register before loading the actual time into the counters. loading of illegal states may lead to a temporary clock malfunction. 1997 jul 15 13 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 fig.11 alarm and timer interrupt logic diagram. (1) if the alarm enable bit of the control/status register is reset (logic 0), a 1 hz signal can be observed on the interrupt pin int. handbook, full pagewidth mbd818 76543210 control/status register (1) alarm interrupt timer overflow interrupt int 76543210 alarm control timer alarm overflow timer control clock alarm alarm timer clock/calendar counter control mode select mux oscillator alarm control register 1997 jul 15 14 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 8 characteristics of the i 2 c-bus the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor. data transfer may be initiated only when the bus is not busy. 8.1 bit transfer (see fig.12) one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. 8.2 start and stop conditions (see fig.13) both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p). fig.12 bit transfer. mbc621 data line stable; data valid change of data allowed sda scl fig.13 definition of start and stop conditions. mbc622 sda scl p stop condition sda scl s start condition 1997 jul 15 15 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 8.3 system con?guration (see fig.14) a device generating a message is a transmitter, a device receiving a message is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves. fig.14 system configuration. mba605 master transmitter / receiver slave receiver slave transmitter / receiver master transmitter master transmitter / receiver sda scl 8.4 acknowledge (see fig.15) the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. each byte of eight bits is followed by an acknowledge bit. the acknowledge bit is a high level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges must pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. fig.15 acknowledgment on the i 2 c-bus. mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master 1997 jul 15 16 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 9i 2 c-bus protocol 9.1 addressing before any data is transmitted on the i 2 c-bus, the device which should respond is addressed first. the addressing is always carried out with the first byte transmitted after the start procedure. the clock/calendar acts as a slave receiver or slave transmitter. therefore the clock signal scl is only an input signal, but the data signal sda is a bidirectional line. the clock/calendar slave address is shown in fig.16. bit a0 corresponds to hardware address pin a0. connecting this pin to v dd or v ss allows the device to have one of two different addresses. 9.2 clock/calendar read/write cycles the i 2 c-bus configuration for the different pcf8583 read and write cycles is shown in figs 17, 18 and 19. fig.16 slave address. handbook, halfpage mrb016 101000a0r/w group 1 group 2 fig.17 master transmits to slave receiver (write) mode. handbook, full pagewidth s 0a slave address word address a a data p acknowledgement from slave acknowledgement from slave acknowledgement from slave r/w auto increment memory word address mbd822 n bytes 1997 jul 15 17 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 fig.18 master reads after setting word address (write word address; read data). handbook, full pagewidth s 0a slave address word address a a slave address acknowledgement from slave acknowledgement from slave acknowledgement from slave r/w acknowledgement from master a data auto increment memory word address mbd823 p no acknowledgement from master 1 data auto increment memory word address last byte r/w s1 n bytes at this moment master - transmitter becomes master - receiver and pcf8593 slave - receiver becomes slave - transmitter fig.19 master reads slave immediately after first byte (read mode). handbook, full pagewidth s 1a slave address data a1 data acknowledgement from slave acknowledgement from slave acknowledgement from slave r/w auto increment word address mbd824 auto increment word address n bytes last bytes p 1997 jul 15 18 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 10 limiting values in accordance with the absolute maximum rating system (iec 134). 11 handling inputs and outputs are protected against electrostatic charge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices. advice can be found in data handbook ic12 under handling mos devices. 12 dc characteristics v dd = 2.5 to 6.0 v; v ss =0v; t amb = - 40 to +85 c unless otherwise speci?ed. symbol parameter min. max. unit v dd supply voltage (pin 8) - 0.8 +7.0 v i dd supply current (pin 8) - 50 ma i ss supply current (pin 4) - 50 ma v i input voltage - 0.8 v dd + 0.8 v i i dc input current - 10 ma i o dc output current - 10 ma p tot total power dissipation per package - 300 mw p o power dissipation per output - 50 mw t amb operating ambient temperature - 40 +85 c t stg storage temperature - 65 +150 c symbol parameter conditions min. typ. (1) max. unit v dd supply voltage (operating mode) i 2 c-bus active 2.5 - 6.0 v i 2 c-bus inactive 1.0 - 6.0 v v ddosc supply voltage (quartz oscillator) t amb = 0 to 70 c; note 2 1.0 - 6.0 v i dd supply current (operating mode) f scl = 100 khz; clock mode; note 3 -- 200 m a i ddo supply current (clock mode) see fig.20 f scl = 0 hz; v dd = 5 v - 10 50 m a f scl = 0 hz; v dd = 1 v - 210 m a i ddr data retention f osci = 0 hz; v dd = 1 v t amb = - 40 to + 85 c -- 5 m a t amb = - 25 to + 70 c -- 2 m a v en i 2 c-bus enable level note 4 1.5 1.9 2.3 v sda v il low level input voltage note 5 - 0.8 - 0.3v dd v v ih high level input voltage note 5 0.7v dd - v dd +0.8 v i ol low level output current v ol = 0.4 v 3 -- ma i li input leakage current v i =v dd or v ss - 1 - +1 m a c i input capacitance note 6 -- 7pf 1997 jul 15 19 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 notes 1. typical values measured at t amb =25 c. 2. when powering-up the device, v dd must exceed 1.5 v until stable operation of the oscillator is established. 3. event counter mode: supply current dependant upon input frequency. 4. the i 2 c-bus logic is disabled if v dd 1997 jul 15 21 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 fig.21 i 2 c-bus timing diagram; rise and fall times refer to v il and v ih . handbook, full pagewidth protocol scl sda mbd820 bit 0 lsb (r/w) t hd;sta t su;dat t hd;dat t vd;dat t su;sto t f r t t buf t su;sta t low t high 1 / f scl start condition (s) bit 7 msb (a7) bit 6 (a6) acknowledge (a) stop condition (p) 14 application information 14.1 quartz frequency adjustment 14.1.1 m ethod 1: fixed osci capacitor by evaluating the average capacitance necessary for the application layout a fixed capacitor can be used. the frequency is best measured via the 1 hz signal available after power-on at the interrupt output (pin 7). the frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average 5 10 - 6 ). average deviations of 5 minutes per year can be achieved. 14.1.2 m ethod 2: osci t rimmer using the alarm function (via the i 2 c-bus) a signal faster than 1 hz can be generated at the interrupt output for fast setting of a trimmer. procedure: power-on initialization (alarm functions). routine: set clock to time t and set alarm to time t + dt at time t + dt (interrupt) repeat routine. 14.1.3 m ethod 3: direct measurement of osc out (accounting for test probe capacitance). the pcf8583 slave address has a fixed combination 1010 as group 1. 1997 jul 15 22 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 handbook, full pagewidth mrb018 scl a0 sda v ss osci osco clock calendar pcf8583 '1010' sda scl master transmitter v dd v dd scl a0 1 sda v ss osci osco event counter pcf8583 '1010' v dd v dd sda scl rr v dd (i c-bus) 2 r: pull-up resistor r = t rise / c-bus fig.22 application diagram. 1997 jul 15 23 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 15 package outlines references outline version european projection issue date iec jedec eiaj sot97-1 92-11-17 95-02-04 unit a max. 12 b 1 (1) (1) (1) b 2 cd e e m z h l mm dimensions (inch dimensions are derived from the original mm dimensions) a min. a max. b max. w m e e 1 1.73 1.14 0.53 0.38 0.36 0.23 9.8 9.2 6.48 6.20 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 1.15 4.2 0.51 3.2 inches 0.068 0.045 0.021 0.015 0.014 0.009 1.07 0.89 0.042 0.035 0.39 0.36 0.26 0.24 0.14 0.12 0.01 0.10 0.30 0.32 0.31 0.39 0.33 0.045 0.17 0.020 0.13 b 2 050g01 mo-001an m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 8 1 5 4 b e 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. pin 1 index dip8: plastic dual in-line package; 8 leads (300 mil) sot97-1 1997 jul 15 24 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 unit a max. a 1 a 2 a 3 b p cd (1) e (1) z (1) eh e ll p qy w v q references outline version european projection issue date iec jedec eiaj mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 7.65 7.45 7.6 7.4 1.27 10.65 10.00 1.1 1.0 2.0 1.8 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.45 sot176-1 95-02-25 97-05-22 x 4 8 q a a 1 a 2 w m b p d h e l p q detail x e z e c l v m a 5 1 (a ) 3 a y 0.25 0.10 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.30 0.29 0.30 0.29 0.050 1.45 0.057 0.25 0.01 0.419 0.394 0.043 0.039 0.079 0.071 0.01 0.004 0.043 0.018 0.01 0 5 10 mm scale pin 1 index so8: plastic small outline package; 8 leads; body width 7.5 mm sot176-1 1997 jul 15 25 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 16 soldering 16.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 16.2 dip 16.2.1 s oldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 16.2.2 r epairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. 16.3 so 16.3.1 r eflow soldering reflow soldering techniques are suitable for all so packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. 16.3.2 w ave soldering wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 16.3.3 r epairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 1997 jul 15 26 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 17 definitions 18 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 19 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011. 1997 jul 15 27 philips semiconductors product speci?cation clock/calendar with 240 8-bit ram pcf8583 notes internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1997 sca55 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - sp, brazil, tel. +55 11 821 2333, fax. +55 11 829 1849 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 160 1010, fax. +43 160 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 0044 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580920 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 417067/00/05/pp28 date of release: 1997 jul 15 document order number: 9397 750 02588 |
Price & Availability of PCF8583T
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |